1. Field of the Invention
This invention pertains to semiconductor memory arrays arranged in matrices of rows and columns of memory cells. More particularly, it pertains to the manner in which a row or column containing one or more defective memory cells may be removed from the circuit and a row or column of extra substitute cells fabricated in the array during the manufacturing process can be electrically connected to replace them.
2. The Prior Art
Semiconductor memory arrays are widely used in virtually all facets of electronics technology. Like other integrated circuit devices they are subject to problems caused by defects introduced during the manufacturing process which often render the entire chip containing the defect useless. Recently, however, to provide for situations in which the defects occur in the memory array itself rather than in the peripheral circuitry, manufacturers have began to equip the arrays with spare rows or columns which may be selectively substituted for a row or column in which a defect has rendered one or more memory cells inoperable. The ability to substitute spare rows or columns for inoperable ones has dramatically increased the yield of good circuits, thus increasing the cost-effectiveness of the manufacturing operations.
Typically, the substitution of good redundant rows or columns of memory cells for defective rows or columns is implemented during testing of completed wafers when individual die which have bad cells at one or more address locations are identified. The row or column containing the defective cell or cells is permanently disabled by electrically removing it from the array, and the redundant row or column is conditioned to respond to the address location or locations formerly occupied by the afflicted row or column.
Early redundancy schemes stored the addresses of faulty locations in a memory, such as a ROM, and used the contents of the memory located at the address of the faulty memory cell to enable another substitute cell and disable the faulty location. An example of such a scheme is disclosed in U.S. Pat. No. 3,753,244 to Sumilas. This scheme, however, has proved to be unsatisfactory for today's fast access time requirements, since the extra time consumed by the substitution mechanism is intolerable for some system applications.
Currently, on-chip substitution of good cells for faulty cells in memory arrays is implemented by electrically or physically disconnecting faulty rows or columns of cells from the array, and electrically connecting substitute rows or columns to the row or column address decoding circuitry on the chip in such a manner that each responds to the address bit pattern which formerly selected the faulty row or column. Redundancy is implemented either before or after packaging of the memory chip and has been accomplished by use of one of two mechanisms: vaporization of polysilicon fuses by use of pulses of electrical current, and vaporization of conductor material with accurately focused laser beams.
These methods have proven to be generally satisfactory for the purpose of implementing row or column redundancy in memory arrays. Some of the characteristics inherent in the implementation of such redundancy schemes have, however, presented various drawbacks which must presently be accepted if redundancy is to be used.
Polysilicon fuse redundancy implementation brings with it the need to supply apertures in the vapox glass passivation layer of the memory array, thus presenting the potential for mobile-ion contamination of the on-chip circuitry. In addition, currents on the order of 10-20 milliamperes are necessary to ensure clean and complete vaporization of the polysilicon material comprising each fuse. Thus, the on-chip devices used to supply the fuse-blowing current to the polysilicon fuses must necessarily be large enough to handle current loads of this magnitude. In addition, the presence of vaporized fuse material on the chip surface has been associated with problems, as has the opening in the vapox passivation layer, through which contamination of the chip may occur. Furthermore, since implementation of a single row or column may necessitate the blowing of a number of such polysilicon fuses in memory arrays of larger sizes, practical considerations because of fuse-blowing current requirements have made it necessary to blow only a single fuse at a time. This creates extra human or machine labor time which must be spent in the final manufacturing stages of producing such memory arrays where redundancy is to be utilized.
Laser redundancy implementation, while eliminating the need to employ additional on-chip real estate in the form of circuitry having the current-carrying capacity to blow polysilicon fuses, replaces that need with a requirement for highly specialized and accurate laser equipment. Such equipment is expensive, requires skilled personnel to use and maintain and usually is capable of vaporizing only one target at a time. Moreover, as memory arrays become more dense and line widths grow smaller, beam positioning requirements will necessarily become more critical.